This invention relates to semiconductor devices and, more particularly, to the fabrication of metal-oxide-semiconductor (MOS) devices.
MOS devices in large-scale-integrated (LSI) form are utilized extensively in a variety of practical applications in the electronics field. In particular, such devices of the two-level overlapping polysilicon electrode type have been recognized by workers in the field as especially advantageous for making random-access-memory (RAM) and charge-coupled-device (CCD) chips in LSI form.
The two-level overlapping polysilicon electrode structure is characterized by a high packing density and an advantageous speed-power product. However, these characteristics are achieved at the expense of a relatively complex processing sequence for making the structure. Furthermore, it has been observed in practice that a major limitation on achieving high yield and reliability in such LSI structures is a high incidence of unacceptably low breakdown voltages therein. This problem occurs due to a breakdown in the oxide that is interposed between the polysilicon layers and/or between the bottom of one of the polysilicon layers and the substrate of the structure.
Accordingly, considerable effort has been directed at trying to devise a processing sequence for LSI MOS devices that would produce structures in which the aforementioned low-voltage-breakdown problem would be eliminated or at least substantially reduced. It was recognized that these efforts if successful could significantly improve the yield and therefore reduce the cost of these commercially important devices.